RAT Microcontroller
By Russell Caletena, Josiah Pang, & Nathan Wang | CPE 233 Winter 2018
A functional computer built in VHDL for the Basys 3 according to RAT Architecture
Project Home
View on GitHub
Demos
RAT Assignment 6
RAT Assignment 7
RAT Assignment 8
Hardware Assignment 1
Hardware Assignment 2
Hardware Assignment 3
Hardware Assignment 4
Final Project